Teneika Askew

Analytics Product Manager | AI/ML | Social Entrepreneur | Data Scientist | Mentor | Big 4 | DS4A | Spartan Racer

Teneika Askew is an Analytics Leader with more than 10 years of experience providing analytics, business process improvement and consulting services. She specializes in data analyses around financial, talent and operational data and driving workforce strategies for Fortune 500 companies.

Teneika uses Power BI, Tableau, SQL and Python to create 100% data-driven, innovative insights using organizational data. She also trains colleagues and the communities she serves with open data made available through the DATA Act.

Teneika also has extensive experience with business analysis for commercial, not for profit, and governmental entities. Her strengths are in performing complex analyses to identify and understand processes, gaps and transactions to answer difficult to solve problems.

Awards: Globant US Digital Leader. Women of Color in STEM - Technology All Star Award. Values in Practice. Applaud Awards (3X). Performance and Team Awards (6X). She Rocks the World, Fearless Leader. Diversity & Inclusion Driver Award. Grace Hopper Women of Color in Tech Scholar. People Analytics World Speaker. Society of Women Engineers Speaker. Distinguished Scholar and Honors level in Data Science for All fellowship(s). Top Teaching Assistant.

Certifications: Microsoft Data Analyst, Certified Scrum Master, Tableau Desktop Specialist, AWS Solution Architect. COBIT 5, ITIL, Agile Certified Practitioner and Microsoft Certified Trainer

Fellowships: Data Science for All - Empowerment and Data Science for All - Women's Summit

Recognized as US Digital Leader by Globant in the annual edition of the Globant Awards - Women that Build,  a global recognition that seeks to change the reality of the industry and reduce the gender gap, highlighting professionals who inspire, who build, who lead and help create change. 
http://womenawards.globant.com/3335/Teneika-Askew
This award recognizes innovative women who are leaders in their organizations and who have been impacting change in the IT industry for at least 10 years.

Featured in Business Insider, Tech Crunch and eFinancial.

teneikaaskew.com | @teneikaask_you on Twitter

Group Product Director - Data Science & Analytics Enablement

The consultant has become the client! I've returned as Product Manager and leader in the Navy's first data focused consulting division, Data and Digital Transformation. I will be bringing my entrepreneurial spirt to build, launch and direct the Data Science as a Service and Analytics Enablement portfolio of products and services.

Stack: Databricks, AWS

California Polytechnic State University (Cal Poly)

NSF-Funded Project: "Assessing the Profession of Ethical Technology for the Future of Tech Work"

- Collected and curated data from various job sites focused on ethical technology roles
- Cleaned and prepared datasets for analysis, ensuring data accuracy and consistency
- Conducted exploratory data analysis (EDA) to identify key trends and insights
- Analyzed the data to assess the evolution and future direction of ethical technology roles in the tech industry

Consultant data science

University of California, Berkeley

Graduate Student

Microsoft

●	Enhanced Network Reliability and Innovation: Creatively developed and implemented process improvements utilizing Microsoft Azure's capabilities to enhance operational efficiency and reliability across network architecture projects. Optimized network performance and infrastructure through innovative approaches and strategic planning.
●	Reduced Annual Interruption Rate (AIR) with Proactive Network Management: Monitored, managed, and communicated various fault codes causing major disruptions in the data center network infrastructure. Demonstrated accountability and innovation by identifying and retaining functional FPGA devices, reducing the FPGA replacement rate to less than 5%, thereby improving cost efficiency and network reliability.
●	Advanced FPGA Efficiency and Service Orientation: Configured servers within our network architecture for networking and storage with a creative approach using Microsoft Azure tools to proactively identify and resolve FPGA issues before code release. This process not only saved months of effort but also significantly improved FPGA efficiency, showcasing a commitment to service-oriented solutions and enhancing network performance.
●	Innovative Debugging Techniques: Captured several FPGA cards from data centers for detailed analysis and debugging by Microsoft and third-party vendors, enhancing product reliability and customer satisfaction through creative problem-solving.
●	Root Cause Analysis for Manufacturing Processes: Provided thorough analysis of manufacturing logs to identify the root cause of unhealthy DRAM, driving accountability and continuous improvement in production processes.
●	Enhanced Diagnostic Processes: Captured and analyzed PCIe traces of suspected FPGA devices, employing innovative and service-oriented techniques to ensure product reliability and improve service delivery.

Senior Engineer

QLogic

Qlogic Ethernet adapter representative to the Dell networking group.  Provided defect management, technical support, schematic and PCB layout design review, and product testing of the Qlogic Ethernet adapters for the multitude of Dell server platforms.
	• Ensured that defects were tracked in both the Qlogic and Dell bug tracking tools.
	• Discussed defects in weekly meetings and ensured that defects were transitioned properly when fixed
	• Reviewed design specifications to ensure adapter compliance.
	• Reviewed schematics and PCB layouts for the Dell Ethernet adapters designed by QLogic.
	• Conducted issue reproduction using Dell server platforms when adapter issues were reported.
	• Coordinated, discussed and helped introduce Qlogic design wins within Dell
	• Provided support and fielded questions regarding the Qlogic Ethernet adapters for Dell's customers 
	• Designed scripts to aid in the testing of the adapters
	• Brought to completion several joint Qlogic/Dell projects

Principal Engineer

Dell

Provided technical support, schematic and PCB layout design review, and testing of several network interface cards and server blade platforms.  Managed audit testing of several components for the network interface cards.
- Team representative as platform interface for several of the server blade platforms.
- Coordinated and provided team feedback to platform design documents.
- Reviewed schematics and PCB layouts for the network interface cards and server blade platforms.
- Conducted basic testing and provided support to internal teams and external vendors during the unit, product and system test cycles of the network interface cards and server blade platforms.
- Monitored issues and routed as appropriate to the network interface card internal and external teams.
- Managed and conducted audit, bit error rate and traffic stress testing of several blade network interface cards and server blade platforms.
- Tracked hardware design requirements to ensure that deliverables were met on time.
- Designed several scripts and Excel macros to improve team productivity and drive improvements within and outside of my team.

Alcatel-Lucent Bell Labs Ventures

Provided technical support and direction for the specification, design, schematic entry and PCB layout of a Wifi (802.11a/b/g/n) radio module in the AMC form factor, and a rugged chassis housing the radios. 

— Tested and characterized the WiFi radios in a lab environment and in field tests.  Implemented in Excel a version of the COST Hata Model to characterize the radios.  Characterization involved the use of lab and field spectrum analyzers.
— Performed basic unit and system testing of the backplane and power circuits for the rugged chassis according to system test plans.
— Conducted additional characterization tests for external WiFi and WiMax radios in a lab environment and field performance tests.

Architected, managed, and maintained lab environments; designed in VHDL, simulated using ModelSim, and lab tested FPGA devices; and performed schematic entry, PCB layout, simulations and tested hardware designs for the prototype team of a research group.

	Contributed to design, code (in Java), and test of a GUI interface for a diagnostic tool of an IPTV network.
	Designed in Java the GUI interface for a packet sniffer tool that monitored proprietary video streams for a government funded NIST project titled Video enhanced DSL.  The Project resulted in an Alcatel-Lucent Patent of which I am a co-inventor.
	Designed an FPGA used in a resilient packet ring (RPR).  The FPGA, a large Altera BGA, converted RPR frames in the SPI 4.2 format to Gigabit Ethernet frames by incorporating IP cores into the design and using state machines to do flow control and scheduling.  The design resulted in an Alcatel-Lucent Patent of which I am a co-inventor.
	Designed an FPGA that implemented several classes of service queues and delivered Gigabit Ethernet frames to a dual bus optical ring when empty slots were detected in the ring.  The project was an international collaboration with France and Germany.
	Designed a 2.5Gb/s module for a Terabit optical router using the Cadence Allegro tools.  Conducted signal integrity analysis using the Allegro SpecctraQuest tool and performed unit tests according to test plans.  The project was an international collaboration with France and Germany.

Alcatel

Used the Cadence Allegro tools for schematic entry, layout, and signal integrity analyses of several board modules used in an optical cross connect switch.  Brought up modules and performed unit testing with oscilloscopes, spectrum analyzers, and SONET test equipment.  Conducted CPK analysis using voltage and temperature extremes.

	Designed an OC48 line card that used high speed optics and custom Asics to convert the 2.488Gb/s data down to 48 STS1 streams.
	Designed a cross point module located in the first, second and third stages of a Clos matrix.  The module uses an onboard processor to interpret logical connections from a level 2 processor and make appropriate connections between stages.
	Designed a stratum 3 clock module used in a cross connect switch.

Electrical Engineer

United States Navy

Machinist Mate 2nd class, E5, Norfolk Naval Base

Machinist Mate 2nd Class

Having recently graduated with a master's degree in data science from UC Berkeley's MIDS program in May 2024, I am passionate about applying my newly acquired expertise in data science to innovative and impactful projects. My proficiency in various tools and languages, including Python (Pandas, Numpy, Matplotlib, Seaborn, ggplot, iPython), R (RStudio, ggplot2, dplyr, plotly), Git/Github, and Jupyter notebooks, enables me to analyze data, create powerful visualizations, and utilize machine learning techniques effectively. As part of my capstone project, I explored retrieval-augmented generation technologies using Jeopardy questions, integrating 470,000 clues across 39 seasons, which enhanced my ability to handle large datasets and develop data-driven solutions.

Over my two-decade career as an engineer at esteemed companies such as Alcatel-Lucent (Nokia), Dell, QLogic, and Microsoft, I have developed a robust skill set in engineering high-speed digital and analog circuits, FPGA devices, network adapters, and servers. My role often required me to be a hands-on, team-focused problem solver adept at intricate challenges in engineering design and testing. For example, I improved cost efficiency by maintaining FPGA devices in working condition, reducing the FPGA part replacement rate to less than 5%.

I am eager to leverage my extensive background in engineering along with my data science skills in my next role as a data scientist or applied scientist. This unique blend of experience equips me to collaborate effectively with talented teams to drive innovation and extract actionable insights from complex datasets.

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Teneika Askew

Gerardo A. Gonzalez

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